Thursday, April 24, 2008

[HiPerCoPS] FFT

To test the reconfiguration mechanism of my simulator, I'll use a 32x32 cell device and implement an FFT circuit. These are the modules that comprise the FFT:
  • 4x4-cell multipliers (12)
  • 2x4-cell adders (11)
  • 2x4-cell subtractors (11)
  • 4x4-cell memories (8)
The experimental variable will be the number of faults, starting at zero and increasing by one until the system can not longer be mapped to the device. The dependent variable will be the percentage of time that the system is unable to be mapped to the device (the "failure rate").

The tests will be performed on a number of versions of my simulator:
  1. No fault avoidance. The placer simply maps modules without knowing/caring if a cell is faulty or not.
  2. Simple fault avoidance. Modules are mapped in the order that they were added to the device, avoiding faults.
  3. Size-aware fault avoidance. Modules are mapped starting with the largest and ending with the smallest, avoiding faults.
  4. GPD fault avoidance. Simple fault avoidance, but faulty cells can be used if the desired functionality is still present.
  5. GPD size-aware fault avoidance. Size-aware fault avoidance, but faulty cells can be used if the desired functionality is still present.
Of course, it will be important to automate this test. Some simple loops should do it though. I'll run a few tests by hand to decide how long each trial takes. Based on that information (and how much time I have at my disposal), I'll decide how many trials to run for a given number of faults. Somewhere between 10^3 and 10^4 trials for a given number of faults per simulation version should suffice, I would think.

Before I move on to the experiment, though, I need to investigate the phenomenon of "pseudo-clustering." Dr. Delgado told me that modern fault models tend to group faults in bunches rather than disperse them equally across a system. Apparently, this model is a closer approximation to the real world. One thing to consider, though, is whether pseudo-clustering is likely to occur in our architecture.

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